VLSI Encyclopedia

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COVID-19 lockdown !!

Invest time to look at some basics.

SystemVerilog Event Regions, Race Avoidance & Guidelines

www.sunburst-design.com

Quiz of the day!!
The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line

Submit your answer with explanation if possible.

COVID-19 Lockdown! A good paper to read.
SystemVerilog - Is This The Merging of Verilog & VHDL?

http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_SystemVerilog_VHDL.pdf

Feel free to post any comments or questions you have.

www.sunburst-design.com

Quiz of the day.!!
A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Post your answers with explanation. Final answer will be explained at end of the day.

Question of the day by Kumar Layek

Q: A, B, C are the inputs to a FULL ADDER, if the value of the SUM = C' (i.e C complement), then what will be the value of CARRY = ???

Low power design techniques. Useful for the designers who will be working on IoT SoC's. Future posts will cover more on UPF and low power verification techniques. Please comment if you need detailed post on any relate topic.

Low Power Design Techniques In today's IOT (Internet Of Things) world there are various wearable/Portable smart devices coming up in the market which are battery operated. These devices also need to be Power efficient such that it can run on battery for a long time. And here the concept of Low Power Design comes into existence...

RIP Professor Stephen Hawking. You will be always remembered for your incredible contribution in physics.

UVM Interview Questions - 5
What is virtual sequencer and virtual sequence in UVM?
How set_config_* works?
What are the advantages of uvm RAL model ?
What are the different override types?
Explain end of simulation in UVM?

UVM Interview Questions - 5 System Verilog UVM Interview Questions. Interview Question related to UVM and OVM methodology with answers.

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 – 8, 2017. In a departure from previous years, both Symposia (VLSI Technology and VLSI Circuits) will be held on a fully overlapping schedule from June 6 – 8, preceded by Short Courses on June 5.

The deadline for paper submissions to both Symposia is January 23, 2017. Complete details for paper submission can be found online at: http://vlsisymposium.org/authors.html

2017 VLSI Symposia on VLSI Techology and Circuits VLSI Symposia 2017 on VLSI Technology and Circuits to be held at Kyoto, Japan from June 5 to 8, 2017.